Bevan Baas

Now at UC Davis

Assistant Professor

Department of Electrical and Computer Engineering

VLSI Computation Lab

University of California

Davis, CA 95616

My web page

Stanford Office:

Packard 025

STARLab - EE Department

Stanford University

Stanford, California 94305-9515 USA

Email:

Please click here

Phone:

650-725-1638

650-723-1024 (lab)

650-723-9251 (fax)

Advisors:

G. Leonard Tyler

Teresa Meng

Kunle Olukotun

Jim Burr

Formerly: Allen Peterson

Research

Research Interests

• High-performance and energy-efficient computation
• Digital signal processing
• VLSI design
• Fast Fourier Transform processors, algorithms, and architectures
• Ultra Low Power CMOS

Publications

Other work

• SPIFFEE: an energy-efficient single-chip 1024-point FFT processor.
• Some chips I've designed:
  • Spiffee1: the first fabricated SPIFFEE processor. [die photo]
  • Srambb: a 128 x 36bit low-power SRAM. A few slides (596KB compressed ps) [die photo]
  • ULP Accumulator 1: a low-voltage memory/adder test chip. Chip plot (55KB compressed ps)
  • ULP Accumulator 2: a low-voltage memory/adder test chip. A few slides (586KB compressed ps) [die photo]
  • Multbb: a 20bit pipelined full-array multiplier. [die photo]
  • MTC: MCM Test Chip.
• VLSI & Sig. Processing conferences
• This work has been supported by NSF, NASA-GSRP, and AISES-GE fellowships.

Education

Ph.D.,

Stanford University (February, 1999)
Dissertation: "An Approach to Low-Power, High-Performance, Fast Fourier Transform Processor Design."
Oral Defense: Abstract, Slides(440KB pdf)

MS,

Stanford University

BS,

California Polytechnic State University

--,

Westmont College

Last update: July 24, 2007