In the mid 90s, the group developed VLSI chips by Bevan Baas, Gerard Yeh, Yenwen Lu, and Masataka Matsui.
Current ULP researchers are Vjekoslav Svilan and Jawad Nasrullah.
We have measured digital CMOS circuits operating error-free at supply voltages down to 117mV at room temp and 40mV at 77K.
A team of graduate students I have been working with in STARLab (Bevan Baas, Yen-Wen Lu, Masataka Matsui, and Gerard Yeh) has fabricated three large (up to 500K fet) chips for use in a variety of tunable, low threshold CMOS processes. We have measured speeds in excess of 100MHz at supply voltages below 400mV at room temperature in a 0.35um technology. Bevan's chip is an FFT engine, Gerard and Yen-Wen's is a motion estimation engine, and Masa's is a 32x32-bit multiplier.
Results of this research include a 0.35um process that achieves 1.5x the performance and half the power dissipation at Vdd=2.0V that the standard process achieves at Vdd=3.3V; the same performance and 1/10 the power dissipation at Vdd=0.8V; and half the performance and 1/100 the power dissipation at Vdd=0.4V.
Circuits tested include: 1) A 32x32-bit multiplier functional down to Vdd=150mV; 2) SRAMs functional down to Vdd=170mV; 3) A divider circuit functional down to Vdd=85mV.
For more information, check out the ULP Group Home Page.
We are developing a process for fabricating ultra short channel transistors using standard lithography. So far we have succeeded in making transistor gates at 0.18um, 0.090um, 0.045um, 0.0225um, and 0.0113um using a 1.25um-resolution stepper. The measured variation in channel length of these structures is less than two percent, considerably better than the 20 percent or so variation normally associated with standard gate lithography.
Thanks to Emmanuel Crabbe for inviting me, Mark Rodder and Bill Frensley for picking me up at the airport, and everyone at the conference for stimulating discussions. The DRC97 web page is here.
I also gave seminars on topics in low power at the University of Trondheim on Monday Oct 23 from 10:15-12:00, and at the University of Oslo on Thursday Oct 26 from 12:15-14:00. Here is the abstract. My host in Trondheim was Trond Saether. My host in Oslo was Tor Sverre Lande (Bassen).
I also played a few tunes at the conference dinner Wed evening with Tormod Njolstad, a researcher at U. Trondheim and an excellent bass player.
I also gave a paper on "Cryogenic ultra low power CMOS" 9:55am Wed Oct 11. Here are my slides.
Other ULP papers at the conference: Masa Matsui's paper "A low voltage 32x32 bit multiplier in dynamic differential logic", 4:55pm Mon Oct 9, and Zongjian Chen's paper "Low threshold voltage 0.25um MOSfets for low power applications", 9:05am Wed Oct 11.
(obsolete)
I play trombone in the "K.A. Wonton Little Latin Big Band", a 10-piece Latin Jazz band playing a wide range of high energy original compositions and arrangements. Cofounded by Erik Rosenquist and Jose Bowen in 1988, the band features Ed Morrison and Dave Brigham on trumpet, Erik on alto sax, me and Steve Kohlbacher on trombone, Dan Filip on piano, Jack Marshall on bass, Wally Schnalle on drums, and Mio Flores and Tom Wieske on percussion.
Here is our upcoming schedule (updated periodically):
.. Band in hibernation while Erik adjusts to being a Dad.
Baseline ULP:
For the best introduction to ULP, read NASA91, followed by ICCD91, then HotChipsV, then ISSCC94, then SLPE95. The early papers focus on subthreshold digital logic; later ones place more emphasis on performance.
The Vail95 slides, together with the DAK95 slides and the DRC97 slides, form the most complete reference.
Anyone is welcome to re-use any of this material as long as it is appropriately referenced.
** ULP CMOS ***
% SLPE95 paper, slides
@inproceedings (Bur95c,
title = "{Cryogenic ultra low power CMOS}",
author = "James B. Burr",
booktitle = SLPE,
year = 1995, pages = "9.4")
% Vail95 slides
@inproceedings (Bur95b,
title = "{High performance, low-voltage CMOS}",
author = "Jim Burr",
booktitle = "IEEE Computer Elements Workshop", note = "Vail, Co",
year = 1995, month = jun, pages = "1.c.1-1.c.75")
% Recife95 slides
@inproceedings (Bur95a,
title = "{Stanford ultra low power CMOS}",
author = "Jim Burr",
booktitle = IV Brazilian Microelectronics School",
year = 1995, month = jan)
% ISSCC94 text, slides
@inproceedings (BS94,
title = "{A 200mV encoder-decoder circuit using Stanford Ultra
Low Power CMOS}",
author = "James B. Burr and John Shott",
booktitle = ISSCC,
year = 1994, month = feb)
% 1993 IEEE Telecomm Workshop slides
@inproceedings (Bur93d,
title = "{Stanford Ultra Low Power CMOS}",
author = "James B. Burr",
booktitle = "IEEE Workshop on VLSI in Communications",
year = 1993, month = sep)
% 1993 IEEE Low Power Workshop slides
@inproceedings (Bur93c,
title = "{Stanford Ultra Low Power CMOS}",
author = "James B. Burr",
booktitle = "IEEE Low Power Workshop",
year = 1993, month = aug)
% HotChips V paper, slides
@inproceedings (Bur93a,
title = "{Stanford Ultra Low Power CMOS}",
author = "James B. Burr",
booktitle = "Symposium Record, Hot Chips V",
year = 1993, month = aug, pages = "7.4.1-7.4.12")
% HotChips Video
@inproceedings (Bur93b,
title = "{Stanford Ultra Low Power CMOS}",
author = "James B. Burr",
booktitle = "University Video Communications",
year = 1993, month = aug)
% ICCD91 paper, slides
@inproceedings (BP91b,
title = "{Energy considerations in multichip-module based
multiprocessors}",
author = "James B. Burr and Allen M. Peterson",
booktitle = ICCD,
year = 1991, pages = "593-600")
% NASA91 paper, slides
@inproceedings (BP91a,
title = "{Ultra low power CMOS technology}",
author = "James B. Burr and Allen M. Peterson",
booktitle = "NASA VLSI Design Symposium",
year = 1991, pages = "4.2.1-4.2.13")
@unpublished (Bur94, paper
title = "{Cryogenic ultra low power CMOS}",
author = "James B. Burr",
year = 1994, month = may, note = "Symposium on Low Power Electronics")
** neural nets **
@inproceedings (Boltz93,
title = "{Digital Boltzmann VLSI for constraint satisfaction
and learning}",
author = "Michael Murray and Ming-Tak Leung and Kan Boonyanit
and Kong Kritayakirana and James B. Burr and Gregory J. Wolff
and Takahiro Watanabe and Edward Schwartz and David G. Stork
and Allen M. Peterson",
booktitle = NIPS,
year = 1993, month = Dec)
@unpublished (Bur93e, slides
title = "{Building silicon brains}",
author = "James B. Burr",
booktitle = "World Science Fiction Convention",
year = 1993, month = sep)
@inproceedings (MB92,
title = "{Scalable deterministic Boltzmann machine VLSI
can be scaled using multi-chip modules}",
author = "Michael Murray and James B. Burr and David G. Stork
and Ming-Tak Leung and Kan Boonyanit and Gregory J. Wolff
and Allen M. Peterson",
booktitle = "Application Specific Array Processors",
year = 1992, pages = "206-217")
@incollection (Bur92, chapter
title = "{Digital Neurochip Design}",
author = "James B. Burr",
booktitle = "Digital Parallel Implementations of Neural Networks",
editor = "K. Wojtek Przytula and Viktor K. Prasanna",
publisher = "Prentice Hall",
year = 1992)
@incollection (Bur91, chapter
title = "{Digital Neural Network Implementations}",
author = "James B. Burr",
booktitle = "Neural Networks: Concepts, Applications, and
Implementations, Volume 2",
editor = "P. Antognetti and V. Milutinovic",
publisher = "Prentice Hall", pages = "237-285",
year = 1991)
@unpublished (Bur91b, paper
title = "{Energy, capacity, and technology scaling in digital
VLSI neural networks}",
author = "James B. Burr",
year = 1991, month = may, note = "NIPS91 VLSI Workshop")
*** MCMs ***
@inproceedings (Bur91a, paper, slides
title = "{System-wide energy optimization in the MCM environment}",
author = "James B. Burr and James R. Burnham and Allen M. Peterson",
booktitle = "IEEE Multichip Module Workshop",
year = 1991, pages = "66-83")
** Max-time statistics **
@inproceedings (Bur88, paper
title = "{Advanced simulation and development techniques}",
author = "James B. Burr",
booktitle = "IREE 7th Australian Microelectronics Conference",
year = 1988, pages = "231-238")