Measurement, Modeling, and Control of Variable Vdd/Vth CMOS Systems
Department of Electrical Engineering, Stanford University
The performance of many modern VLSI applications is limited by power constraints rather
than maximum achievable performance levels. For many circuit styles, reducing the supply voltage (Vdd) dramatically
reduces power dissipation. In order to maintain performance with lower supply voltages, however transistor threshold
voltages (Vth) must also to be lowered, resulting in increased leakage power. Interestingly, there exist optimum supply
and threshold voltages which satisfy performance demands while minimizing total power dissipation. These optimum
voltages vary dynamically and are dependent on parameters such as circuit activity, logic depth, temperature, clock
frequency, local and global transistor variations, and other device characteristics.
Traditional, standard CMOS circuits operate at fixed supply and threshold voltages. More recently, variable supply
voltage CMOS designs have been introduced. Variable supply, body-bias tunable Vth CMOS technology enables adjustments
of both the supply and threshold voltages. In this dissertation we measure and model advantages of variable Vdd,
body-bias tunable Vth CMOS systems and design control mechanisms necessary to put those systems into their most
optimum energy state.
Comparison of measured energy and performance of an existing 32-bit multiplier design fabricated in both standard
CMOS and in a low-Vth body bias tunable CMOS technology provides evidence that low power designs employing variable
Vdd and Vth are feasible. In 0.35 um technology, the tunable design can be optimized to achieve a better than 5 times
reduction in power dissipation over the standard CMOS implementation, and is able to operate with up to a 38% faster
clock rate. In addition, a new modeling tool enables quick design comparisons between various Vdd/Vth techniques.
This model compares four design approaches and accounts for various inputs and effects such as average logic depth,
circuit activity, local and global variations and temperature. Finally, four alternative control approaches which
dynamically adjust both the supply and body bias voltages seek optimum balance of active and leakage power by taking
full advantage of variable supply, low Vth body-bias tunable CMOS technology. These four control mechanisms use either
a critical path replica or embedded speed sensors to track the circuit speed and either an Ion/Ioff circuit or well
voltage perturbation to adjust the transistor threshold voltages. Two of the four achieve near-optimum energy
performance. We show that the control mechanism using embedded speed sensors in combination with the well voltage
perturbation technique is the most energy efficient, but also the most difficult to implement.