[stanford_seal] Ultra Low Power Technology Group

The Ultra Low Power Technology Group in the Department of Electrical Engineering at Stanford University is interested in the study and implementation of VLSI processing that is both low-power and high-performance.

This is done through the radical reduction of supply voltages using chips fabricated in tunable low threshold CMOS processes. Current designs are expected to operate in excess of 100MHz with supply voltages below 500mV at room temperature. Fabricated chips have operated error-free at supply voltages of 125mV with ring oscillators operating at Vdd=70mV at room temperature and Vdd=27mV at 77K.

We are:

Prof. Len Tyler
Jim Burr
Bevan Baas
Jawad Nasrullah
Vjekoslav Svilan
Also see the people page

ULP Chip Gallery

Group Projects

Internal web page

Last update: August 30, 2000.

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