SPIFFEE

SPIFFEE is a full-custom 1024-point single-chip Fast Fourier Transform processor designed for low power operation. The processor operates on 36 bit fixed-point data (18 bits real and 18 bits imaginary). To increase precision, the processor's main datapath is 20-24 bits wide. The datapath computes a complex radix-2 butterfly every cycle -- which includes 4 multiplies, 6 adds, 6 20 bit reads, 4 20 bit writes, and 11 address calculations.

Check out Spiffee1, the first fabricated SPIFFEE processor.

In a 0.5µm ULP CMOS process at a supply voltage of 400mV the chip is estimated to run at over 85MHz with a power of 8mW. This will result in a 1024 point transform being calculated in 61µs with an adjusted energy efficiency over 75 times greater than the previously most efficient known FFT processor.

Also see the FFT Chip Comparison Table which compares various commercial and academic FFT processors.

Here are some more details:

460,000 transistors
The chip contains:
- (8) 128 x 36bit low power SRAMs with hierarchical bitlines
- (4) 16 x 40bit dual ported caches
- (2) 256 x 40bit low power ROMs with hierarchical bitlines
- (4) 20bit x 20bit full array pipelined multipliers
- (6) 24bit CLA adders
- Controller, Voltage controlled oscillator, and test circuitry.
Although the processor is high performance and deeply pipelined, robust circuits were used throughout. Scannable latches are used to allow testing of individual functional units. All circuits (including precharge style) are designed to be operational at arbitrarily low clock frequencies.
All substrate/well ties are routed to pads separately from Vdd/Gnd. This will allow us to tune the thresholds of V_t=0 transistors. In addition, substrate/well ties used in the main memory are routed separately from the rest of the processor.
The I/O interface is clocked independently from the processor's clock allowing high speed operation along with easy testing. The chip is also designed to be fully operational (with lower throughput) with a small number of low speed I/O pins (10 data signals, less than 50 total pins).
Custom level shifting pads were designed that allow the chip core to operate at a lower voltage than the I/O circuitry.
The chip has been designed to operate with a supply voltage below 400mV with V_t=0.
MOSIS scmos design rules were used with one level of poly and three levels of metal.

See Spiffee publications.

This work has been supported by a NASA GSRP fellowship and an AISES GE fellowship.

Keywords: FFT, DFT, chip, processor, CMOS, low power, DSP, high performance, fast fourier transform, discrete fourier transform, fixed point, custom, 1024 point, fast, efficient, single chip, research, R&D, Stanford University

Last update: July 14, 1997