Spiffee1

The first fabricated SPIFFEE processor

• 1024-point complex FFT calculated in:
  • 330µsec while dissipating 9.5mW - with an adjusted energy-efficiency more than 16 times greater than the previously most efficient.
  • 30µsec while dissipating 845mW at a clock speed of 173MHz - which is a clock speed 2.6 times faster than the previously fastest.
• Fabricated in 0.7µm CMOS (L_poly=0.6µm)
• 5.985mm x 8.204mm
• Fully functional on first-pass silicon
• Would you like to use Spiffee chips? If so, I'd love to talk to you. Please write me. Spiffee1 is a 1^st version research chip and isn't quite "commercial ready," but a commercial version may be built if there is sufficient interest.
• Milestones:
  • May 31, 1995: Design completed
  • July 26, 1995: Run taped out
  • November 18, 1995: Wrote 32 words to memory and correctly read data back
  • December 1995: Verified 650 element scan path
  • December 1995: Ran into limitations with the HP8180 and HP8182 testers that limited vector length, voltage ranges over which the pads would run, and allowable data patterns
  • 1996: Co-developed the QDT tester, wrote an irsim<=>serial port interface
  • March, April 1997: QDT tester built, debugged, and working
  • April 24, 1997, 9:35pm: A complex 1024-point FFT was successfully calculated. For proof, see what it did to some common functions.

See Spiffee publications.

Back to main SPIFFEE page.

This work has been supported by a NASA GSRP fellowship, MOSIS, and an AISES GE fellowship.