general information
research groups
radioscience seminars
stanford courses
oral defense abstract
industrial affiliates
Radioscience Seminars

EE 350 Radioscience Seminar
Professor Howard Zebker
Autumn 2003-2004

Date: Wednesday, December 3, 2003
Time: 4:15 PM – Refreshments at 4:00
Location: Bldg. Packard, Room 101

Technology Development for Ultra-Low-Power Circuit Techniques
Jawad Nasrullah
Dept of EE, Stanford University

Ultra-low-power (ULP) circuit techniques incorporating dynamic threshold-voltage control through back-gate bias have promise for leading-edge fine-geometry CMOS. To date, application of ULP is usually limited by fabrication technology. Our implementation approach is to fabricate aggressively-scaled thin-film transistors with back gates in a 3-D compatible IC process. Aggressive scaling of device features is achieved via an edge-defined patterning process. With this approach, nanometer (nm) scale lines patterned in silicon--using 1 Ám optical lithography, with standard materials and standard processing equipment--are compatible with low-thermal-budget processes. For implementation, a chemical vapor deposition (CVD) process defines spacers around optically registered edges; this step is combined subsequently with a photoresist mask to pattern underlying layers. Good control of CVD and dry etching enables patterning of features from as fine as 18 nm up to 180 nm. Local critical dimension (CD) variations of up to 7 nm have been observed, based on CD-SEM analysis. Spacer-film roughness, oxide-etch chemistry, and edge-registration lithography contribute to CD variations and line-edge roughness. It is equally important to control surface roughness for films used in the edge-defined process film stacks and/or the ultra-thin body device channels. Analysis of deposited Si and SiO2 film surface roughness indicates that films thinner than about 20 nm should first be deposited more thickly than needed, and then etched back to the desired thinness; use of a binary etch process improves roughness control. Finally, insulated back-gated FET devices patterned with an edge-defined process perform electrically as expected with regard to threshold-voltage tunability. Statistical threshold-voltage variations are observed in these devices, however. This variation is attributed plausibly to polycrystalline-silicon grain-boundary charge traps, and to channel shortening due to enhanced dopant diffusion along grain boundaries. These problems are under further investigation.